ASIC Design Engineer (Sr. Staff or Principal Level)

San Diego, CA 92127

Posted: 05/08/21 Employment Type: Direct Hire Industry or Function: Engineer Job Number: JM042321-1 Compensation: $160,000- $180,000 annual plus robust benefits package

Job Description

The Senior Staff, Principal ASIC Design Engineer is responsible for designing ASIC and FPGA used in cellular connectivity products. Working with cross functional engineering teams (software, hardware and system) on architecture and system validation. Responsible for ASIC and FPGA design, simulation, timing analysis, test, prototyping and qualification.  This is a “front end” Engineering position, with experience designing cellular modems, CPU subsystems and peripherals or interfaces such as USB, Ethernet, JESD204B as the main focus.  The role must also interface with ASIC backend team, FPGA Synthesis - the backend is outsourced.  

Job Duties:

  • Architecture, design, verification and validation for connectivity products’ ASIC and FPGA
  • Support other teams during the development of products
  • Proactively identify problems early
  • Deliver on schedule

Tools Used:

  • System Verilog
  • Perl, awk, sed scripting
  • GIT version control system
  • C language
  • Cadence simulator, linter and code coverage
  • Prime Time static timing analysis
  • Xilinx & Intel FPGA tools
  • Oscilloscope

Job Requirements:

  • Minimum of a Bachelor’s degree in Engineering or related field is required. Preferred is Master’s degree in Science, Engineering, or related field.
  • Minimum of 10 to 15 years of ASIC & FPGA design.
  • Proven successful experience completing multiple ASIC tape-out, preferably as a technical chip leader.
  • Proven successful experience completing multiple FPGA designs for ASIC prototyping and products.
  • Experience working with other teams (software, hardware, and system).
  • WCDMA, LTE & 5G cellular modem
  • CPU cores such as RISC V, Altera Nios II, Open Core OR1200, ARM cores etc.
  • Experience with design and/or verification of interfaces such as:
    • USB
    • Ethernet
    • SPI, UART, I2C
    • parallel LVCMOS interfaces
  • High speed transceivers interfaces such as:
    • CPRI
    • JESD204B
  • Good knowledge of C language, for the purpose of writing test code for ASIC and FPGA validation
  • Good scripting capability with Perl, Awk, sed etc.




  • Generous benefit package, including competitive salary







Meet Your Recruiter

Jill Martinelli

I have the coolest job in the world! Defined: Recruit (1635-45); < French, stem of recruter, derivative of recrue new growth. I love this definition – it’s focus is on new growth. I help individuals, departments and organizations grow! As an industry generalist I have the opportunity to learn about the latest technology in real time and converse with the most intelligent, creative and educated people in their respective fields. What a gift to be able to learn from my clients and candidates who keep me current and ahead of industry technology trends while helping them grow their careers and teams. I cut my recruiting teeth by staffing Qualcomm Assemblers (I earned a Soldering Certificate – trained by Qualcomm’s then Production Manager) to Engineering and everything in between. I believe my greatest strength lies in my ability to learn a company and its products as if I work for them- because I do! This leads to the opportunity to build their teams across multi-disciplines, Engineering, Sales & Marketing, Quality, Materials, Operations and Management/C-Level, across multiple industries. (Medical device, Electronics, Green technology, DOD and Scientific) I have helped numerous startups as well as mature corporations grow their teams. My network of contacts has been built over 25 years and has proved invaluable as a resource in finding the best of the best for companies and candidates. Originally from Buffalo, NY (Go Bills!) I earned my BS from SUNY Oswego in Elementary Education (comes in handy as I do a lot of coaching!)
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